Intel's Stimulus Plan

Because the plain of rest of the world right tiny room, Intel will spend $7 billion to reduce its pieces.

The walk of technology does not await any business cycle. Or thus believe people at Intel Corp., which envisage to roughly pour $7 billion during the two years to come in factories from building to the United States which will make the next generation of the chips.

Synchronization is awkward. In Intel January announced an unhappy quarter, with sales in bottom of 23% (to $8.2 billion) and the trading income in bottom of 49% (to $1.5 billion) of the corresponding period one year ago. The market for GCV shriveling. Intel of the 'shares of S have 27% fallen with $14.69 during the last year.

Nevertheless, the senior officer Paul S. Otellini from Intel had a brief answer once asked whether Intel will measure its construction behind envisages if the company 'the exchange stocks of actions of S drops more: Nope.

Intel hopes on profits of effectiveness to tighten transistors together so much narrowly that billion adjustment on a piece of nail-size. These profits take two forms: less consumption of electricity and inexpensive per unit of capacity for treatment. A transistor the 'components of S will measure 32 nanometers through, 71% of the size of today 'of S 45 circuits of nanometer.

Tiny pieces must be made in big spaces. Into Oregon Intel will convert a factory of development (with tests) into factory with strong flow of production. Into Arizona Intel will transform two factories into simple which have a clean room of 320.000 square feet. That 's about the size of the Acropolis of Athens. A factory of Mexico will also obtain one to remake to become the world the 's larger clean class-a part, without more one 0.5 point of nanometer of dust per cubic foot.

Inside these arenas the key to establish the next generation of the tiny pieces is a technique known under the name of lithography of immersion. To include/understand how that functions, it helps to know of the pieces are engraved with the etching on silicon. Silicon gaufrettes are covered in a chemical brew called photosensitive varnish. Lumi�re is radiated with the gaufrette by a mask of photograph cut out with parts of the design of circuit. Where the light contacts resistance, the chemicals turn sticky and can be removed. Where there is no resist, silicon dioxide left engraving with strong water acids in the next stage. The sculpted layer becomes the base for still another stage. More layers of silicon dioxide and other materials are developed on the engraved layer with the etching. The process obtains then repeated, on several occasions.

Nowadays the wavelength of the light employed starts with 193 nanometers. To avoid moving in the twilight zone of the extreme ultraviolet lithography (or, worse, of x-rays), manufacturers of integrated circuits must narrow the light