Intel's silicon brick roadmap

| Sunday, April 26, 2009

Intel gave us the lucky notches a launching of post-Nehalem giving of the instructions to the overall aspects of its short-term roadmaps of processor. Here 'fast excursion of SA by the synopsis of the matters.

Intel reassured us that it could see Moore 'progression of law of S being maintained for ten more approximately years with the contractings of process and other developments in its roadmaps. Inexorable rise in the transistor counts on the matrices, 731 million with quadruple-cores of Nehalem, should continue above this period. The great exit is people including/understanding how to employ parallelism.

Processors of waiter of Intel

Intel 'of the platforms of waiter of S groups covers several markets: high-output computer (the HPC), computer of Internet and the cloud, migration centres of RISC, storage and centre computer virtualized. Its constitutive blocks are central processing units of treatment, chipsets, the LAN, SSD/RAID, panels/KDKs and software. Its platforms of processor are Itanium (9000 series) for the waiters mission-critical, Xeon 7000s for the waiters at end high of company, Xeon 5000s for the traditional waiters of quadruple and duel-casing of company, and Xeon 3000s for the simple waiters of SME of casing. Obviously Xeon 7000s and Itanium compete with each one with the 'eyes of S but in Intel 's.

Much was done in Intel conceiving in devices support Virtual Server to obtain if all goes many apps functioning in virtual machines functioning as quickly as of the apps functioning in a non-virtualized waiter.

We had fast gambades by Xeon 5500 of the 'devices of S and then obtained with not very interesting, Westmere-EP, the processor of the second generation of Nehalem (5000 series) built with a forthcoming process 32nm. Westmere is basically a contracting of Nehalem on the process 32nm.

It will have six cores, improvements of hiding-place and better energy efficiency, and will be announced in 2010. Also it will be casing-compatible with the 5500, thus the suppliers of waiter can employ the councils of waiter and the existing processors of Westmere of catch directly inside. The graph showed a bus of NCV 2 Westmere binder with a transistorized disc of Intel X25-E, and a controller of Intel 10GbitE.

Intel has an analogy of tick-tock for its developments of technology. With drill is a contracting of process employing current microphone-architecture. The last drill was the movement with transformer technology 45nm current. With tock is the introduction of a new processor microphone-archictecture and Nehalem is the last event of tock.

It will be followed drill 32nm which will be in their turn followed by next microphone-architecture after Nehalem.

On before 7000 the 7400 is 6 a processor of the core 45nm which 's casing-compatible with the 7300 precedents. It will be followed of Nehalem-EX in second half of this year and then Westmere-EX a certain hour later.

Nehalem-EX, built on the process 45nm, is a processor of 8 cores designed for 4 platforms of casing, meaning 64 wire (2 wire/core always). It will employ an extensible interconnection of memory of Intel with shock absorbers and which Intel called the technology of the second generation of input-output with the virtualisation.

There will be technology of VT from Intel in the processor (VT-x), the tiddlywinks (VT-d) and for the network (VT-c). The idea is to obtain these components functioning better together so that the suppliers of waiter go all-Intel instead of employing third chipsets and interfaces of communications. Thus there 's no need for fibre Handle above adaptor Ethernet, a CAN, because these devices of initiating VT plus Intel 'of software FCOE of S will obtain the NIC from Intel 10GbitE squirting outside packages of FCOE at the speed close to wire to the devices direct-attaches.

There will be queues of device of virtual machine (VMDq) to improve the exit by unloading data matching with the NIC. In a waiter virtualized the virtual machine (VM) more or less of maintenance directly with the NIC without having to pass by the hypervisor. (Naturally this different VMs in the cycles from central processing unit of treatment of use of waiter means to carry out the work of FCOE however. For why the doesn of Intel 't goes FCOE-unload is beyond me. It tried to make the same thing with the TCP/IP unload, to say there was not no need, and for pretty lost much this argument.)

Intel presented the migration of cable thus of VMs can be easily transferred between various waiters from Xeon. Previously, notwithstanding the overall compatibility of instruction between 3000s, 5000s and 7000 Xeons, VMs could only be moved between the similar types of processor.

We can await a version of Nehalem of the 3300, probably the 3400 and probably at the end of this year or 2010.

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